1. Field of the Invention
The present invention relates to a semiconductor integrated circuit with a test device comprising a central processing unit (hereinafter, referred to as a CPU), internal memory means (hereinafter, referred to as RAM), a target test circuit (hereinafter, referred to as an user logic section) in which a plurality of flip flop circuits connected one another in a line like a string of beads that are operable as shift registers, and a scan test circuit, that are mounted on a same semiconductor chip.
2. Description of the Prior Art
FIG.1 is a diagram showing a configuration of a conventional semiconductor integrated circuit as a conventional example. In FIG.1, the reference number 101 indicates a semiconductor chip on which a random access memory (RAM) 102, a CPU 103, a user logic section 104 as a target test circuit, and an internal bus group 105 through which the RAM 102, the CPU 103, the user logic section 104 are electrically connected to each other. The reference number 106 denotes an external bus interface (IF) unit for connecting the internal bus group 105 to input/output terminals 107. The reference number 108 indicates input/output terminals of the user logic section 104. The reference number 109 designates a scan clock terminal through which a scan clock signal is provided from a logic tester 113 to the user logic section 104. The reference number 111 denotes a scan-in terminal of the user logic section 104, and 112 indicates a test terminal of the user logic section 104.
FIG.2 is a diagram showing a configuration of a logic tester and the conventional semiconductor integrated circuit shown in FIG.1. In FIG.2, the reference number 113 designates the logic tester connected to the input terminals 108 and each of the terminals 109 to 112 in the conventional semiconductor integrated circuit. The external bus IF unit 106 is used for accessing the external RAM (omitted from the diagram) by the CPU 103 or used for accessing the user logic section 104 or the RAM 102 by an external device (omitted from the diagram) through the internal bus.
Next, a description will be given of the operation of the conventional semiconductor integrated circuit.
In the prior art, in order to easily perform the testing operation for the user logic section 104 incorporated in the conventional semiconductor integrated circuit, the plurality of Flip flops in the user logic section 104 are so made that data items may be written to or read from the flip flops by a scan method. In the scan method, all of the flip flops in the user logic section 104 are connected one another in a line like a string of beads. In the scan test mode, all of the flip flops in the user logic section 104 are performed as a shift register and a plurality of scan data items are inputted to the user logic section 104 through the scan-in terminal 110 and scan results of the user logic section 104 are output to the logic tester 113 through the scan-out terminal 111. It is thereby possible to treat the internal circuit in the user logic 104 as a combinational circuit and possible to achieve a self-diagnose function of the semiconductor integrated circuit. This scan method is widely well known, for example, it is shown in conventional textbooks in a computer design field.
Because the tester for the conventional semiconductor integrated circuit has the configuration described above, in order to perform the test of the user logic 104, it must be required to connect the semiconductor integrated circuit to the tester 113 whose cost is expensive through the terminals 107, 108, and 109 to 112. In addition to this, it must be required to form dedicated test pins only for use in the-scan test in the semiconductor integrated circuit. Furthermore, the number of the test pins formed in the semiconductor integrated circuit is limited in area. Furthermore, in the scan method, it must be required to generate scan clocks corresponding to the number of the flip flops in the user logic section 104 for the readout/write-in of data items in the flip flops. This causes to increase the time of the scan test. In order to decrease the time of the scan test, it may be possible to increase the number of ring-lines of the flip flops as a shift register. However, this scan method increases the number of terminals for testing and increases the size of the configuration of the semiconductor integrated circuit and the configuration of the semiconductor integrated circuit becomes complicated.